Data processor having operand tags to identify as single or double precision

ABSTRACT

A data processor having a memory in which stacks of information are stored. The top two words of an information stack, currently being operated on, are stored in two registers external to memory. An extension register is provided for each of the aforementioned registers to allow the handling of double length information units. The operand words stored in the registers have tag bits as a part thereof which identify the operands as single or double word length information units. Control circuitry is responsive to the tag bits for causing the words to be automatically manipulated or handled as single or double word length information units. A processing unit processes the data stored in the registers.

I United States Patent 1 1 3,593,1 1 1 2 2] Inventors Robert 8. Barton 3,351,913 11/1967 Pine v. 340/1725 Salt Lake City. Utah; 3,331,056 7/1967 Lethin et alm 340/1725 lfl B- Clrlmfl. Amdil; 3,293,616 12/1966 Mullery et 211.. 340/1725 mr Gl n Benjamin 3,286,236 11/1966 Logan et a]. 340 1725 k Erwin 3,251,042 5/1966 King 340/1725 PP 571.621 3,234.519 2/1966 Schohenm. 340/1725 1 1 Filed NW I969 3,045,212 7/1962 Johnson 340/1725 22:23 Primary Examiner-Gareth D. Shaw Detroit, Mich. AImrney-Chnst1e, Parker and Hale Continuation of application Ser. No. 668,460, Sept. 18, 1967, now abandoned.

54 DATA PROCESSOR HAVING OPERAND TAGS T0 K IDENTIFY ASSINGLE 0R DOUBLE PRECISION A clata processor having a memory In which 25 Chin-s H Drawing a; stacks of Information are stored. The top two words of an informatlon stack, currently being operated on. are stored in US. 1 1 t 1 1 1 1 i 1 4 A 1 1 11 two registers exemal to memory An exension register is p III. for each of the aforementioned ggisle s to allow the 9/00 handling of double length information units. The operand [50] Field 340/1725; words stored in he m have lag hits as a pm h f 235/157 which identify the operands as single or double word length information units. Control circuitry is responsive to the tag bits Rem-mm cud for causing the words to be automatically manipulated or han- UNITED STATES PATENTS died as single or double word length information units. A 3,351,917 1 1/1967 Shimabukuro 340/1725 processing unit processes the data stored in the registers.

PATENTED JUL 1 3 |97| SHEET 02 0F 10 PATENTED JUL 1 3 l97| SHEEI 03 [1F 10 PATENTEB JUU 3l9F2 3,593.31?

PATENIEU JUL 1 3 I971 SHEET 07 OF 10 PATENTEU JUL 1 3 Ian SHEET S Q 'N Q DATA PROCESSOR IIAVING OPERAND TAGS TO IDENTIFY AS SINGLE R DOUBLE PRECISION This application is a continuation of application Ser. No. 668,460, filed Sept. I8, 1967 and now abandoned.

BACKGROUND OF THE INVENTION 1. Field of the Invention This invention relates to data processors and, more particularly, to digital data processors capable of operating on single or double word length information units.

2. Description of the Prior Art Prior art data processors are known which read information from memory a word at a time but which are capable of operating on information units having either a single word or two words. Where each information unit has one word it is called "single precision," whereas when each has two words it is called double precision." These data processors accumulate the single word or two words in registers external to the memory.

The prior art data processors are characterized in that information in the instruction itself identifies whether the information unit is a single or double precision and the circuits in the data processing system are responsive to the instruction to handle either a single word or a double word information unit. For example, if information is to be stored from registers into the memory under control of a store operator, the store operator will specify whether the information is a single word in length or a double word in length and the hardware is responsive to the instruction to cause either a single word or two words to be stored in memory.

Such prior art data processors suffer from the disadvantage that the programmer must keep track of the operand structure that he is working on. As a result, the programmer must specify in an instruction whether the information to be operated on is single or double precision. This places a considerable burden on the programmer and causes the program to be longer than it need be if this information were not carried in the pro- In contrast to the prior art, an embodiment of the present invention is a data processing system wherein each operand information unit has a tag which identifies it as single order:- ble precision. The circuitry in this system is responsive to such tag within each operand for automatically handling the operand gs either single or double word information units.

An important advantage of the present invention over the above-mentioned prior art system is that the programmer does not need to worry about the operand structure. The programmer merely writes his program as if the information were all single precision information and the circuitry in the system automatically handles the information in accordance with each instruction. If a particular operand is tagged as single precision, the circuitry merely handles a single word operand. If an operand is tagged as double precision, then two words are handled for such operand. Because of this feature, the programmer merely writes his program designating how data is to be operated on, for example, load registers or store information from the registers into memory or add, etc. The circuitry in the data procemor, using the tags, automatically handles the data in the right manner.

Another advantage of the present invention is that it is easy to apply a program which has already been written to either single or double precision operands because the circuitry of the data processor automatically handles the information in accordance with the program without the need for wial program instructions designating the information has single or double word in length.

SUMMARY OF THE INVENTION Briefly, an embodiment of the present invention in a data processing apparatus includes a combination of register means for storing a first word and sometimes an extension word predetermined tag which identifies an extended word length information unit. Memory means is provided for storing information units from the register means, word by word. Also provided is means operative for transferring a single word between the register means and the memory means and which is also operative in response to said tag identifying an extended word length in an information unit for transferring an extension word between the register means and the memory means. In this manner an extended information unit is automatically stored into the memory means.

An embodiment of the invention also comprises a data processing apparatus having register means for storing a first word and an extension word of an information unit for processing. The information unit has as a part thereof a predetermined tag which identifies whether the corresponding information unit contains an extension word. Means is provided for processing a word stored in the register means and includes means responsive to a tag in an information unit identifying an extension word for automatically proceming the extension word thereof. The extension word is processed together with the first word and in this manner a result is formed having a double word length.

These and other advantages of the present invention will be more fully understood with reference to the following description of an embodiment of the invention.

BRIEF DESCRIPTION OF THE DRAWINGS FIG. I is a general block diagram of a data processor and embodying the present invention;

FIG. 2 is a more detailed block diagram of the embodiment of the present invention shown in FIG. I showing the stack adjusting circuitry;

FIG. 3 is a block diagram of the control unit for the stack adjust circuitry shown in FIG. 2;

FIG. 4 is a flow diagram illustrating the sequence of operation for the circuits shown in FIG. 2 while adjusting information in a stack preceding the execution of a "ADD operator,

HO. 5 is a flow diagram illustrating the sequence of operation for the circuits shown in FIG. 2 while adjusting information in a stack preceding the execution of a "LOAD operaor? FIG. 6 is a flow diagram illustrating the sequence of operation for the circuits shown in FIG. 2 while adjusting information in a stack preceding the execution of a "STORE operatan" FIG. 7 is a detailed block diagrun of the circuits shown in FIG. I for executing an ADD operator," as "STORE operator" and a LOAD operaton" FIG. 8 is a block diagram of the control unit for the circuits shown in FIG. '7;

FIG. 9 is a flow diagram illustrating the sequence of operation of the circuits shown in FIG. I while executing an "ADD operaton" FIG. I0 is a flow diagram illustrating the sequence of operation of the circuits shown in FIG. 7 while executing a "LOAD operator;" and FIG. II is a flow diagram illustrating the sequence of operation of the circuits shown in FIG. 7 while executing a "STORE operator."

DESCRIPTION OF THE PREFERRED EMBODIMENT Refer now to the general block diagram of the data processing apparatus shown in FIG. I and embodying the present invention. The preferred embodiment of the invention is in a computer system wherein information is handled in stacks. U.S. Pat. No. 3,200,379 tiled in the name of P. D. King and assigned to the same assignee as the present invention describes a data processing system which utilizes the principles of a special form of algebraic notation, developed by the Polish mathematician .l. Lukasiewicz, in which all parenthesis are eliminated by having the operator, such as add, multiply,

forming an information unit. Each information unit has a etc., follow theoperandsinvolved in the operation. Theresult is then utilized as an operand in the same sequence. Implementation of this type of notation requires some temporary storage in which operands can be stored on a last in, first out, basis. Such a storage system has been referred to as a stack" storage system because the operands can be considered as being placed in storage by stacking one on top of the other and then removing them in the reverse order, i.e. taking the operands off the top of the stack. The stack of information is partially stored in memory and partially stored in registers external to memory. Referring to FIG. I, it will be noted that words of information are depicted as being stored in memory locations I through I03 of a memory I0. Two more words of the information in that particular stack are stored in an A register 12 and a B register I4. Information is read out of the memory I0 and stored in the memory III in words having a prefixed number of bits. Similarly, the information stored in the A and B registers have the same prefixed number of bits. Thus, the stack which is illustrated in FIG. 1 includes the words of information stored in memory locations I00 through 103 and the two words in the A and B registers. The A register is the top of the stack and the memory location I00 is the bottom of the stack. The other details of such a stack system are described in the above-identified U.S. Pat. No. 3,200,379.

Information is handled in units referred to as single preci sion or double precision. A single precision information unit is one which is one word in length. A double precision information unit is one which is two words in length. A word of a single precision information unit is stored in the B register I4 or the A register 12 and completely defines an information unit. Also single precision information is stored in the memory with one word forming a complete information unit in each memory location. For example, if the stack in memory depicted in FIG. 1 contains a single precision word in memory location I03, a complete information unit is stored in memory location I03. If a double precision information unit is stored then, for example, one word would be stored in memory location I03 and the other in memory location 102. In the latter case, it takes both words in memory locations 102 and I03 to make up a complete double precision information unit.

The two words of a double precision information unit can be stored in either the B register I4 and Y register I5 or the A register I2 and an X register 13. One word is stored in each register.

The content of the B and Y registers form one complete double precision information unit and the content of the A and X registers form one complete double precision informa tion unit. Since the memory stores one word in each memory location the two words making up a double precision information unit are stored in two consecutive memory locations with the least significant word of the two stored in the higher numbered memory location. For example, if double precision information is stored in the stack depicted in memory, the memory of FIG. 1, the first double precision information unit would have the most significant word stored in memory location I00 and the least significant word in memory location 101 and the second double precision information unit would have the most significant word stored in memory location 102 and the least significant in memory location 103.

An important aspect of the present invention is that each information unit itself has a "tag" which identifies whether the unit is a single precision information unit or a double precision information unit. Although the tag might be in each single precision word and in only the most significant word of each double precision word, the preferred embodiment of the invention has the tag placed in each operand word. Thus, in a double precision information unit there is a tag in each of the two words which identifies that that word is a part of a double precision information unit. Thus, each of the words stored in the stack in the memory I0 and each of the words stored in the A, B, X and Y registers has a tag" which identifies whether that word is a part of a single precision information unit or a double precision information unit. The tags of the words are stored in sections 120, 14a, I30, I50 of the A, B, X and Y registers I2, I4, I3 and I5, respectively.

An S register I8, a buffer register I9 and an instruction address counter 26 are used to address the memory to for reading and writing information therein. The S register is used to point at or address the top of the stack in the memory 10. The bufl'er register I9 is used to address other areas of memory from the stack area to bring in information words to the stack. The instruction address counter 26 keeps track of the address of the next operator to be executed.

Consider briefly the operation of the system shown in FIG. I, For purposes of illustration the use of the tag bits for identifying the corresponding information unit as single or double precision is only described for three different types of operators, namely, an ADD operator, a LOAD operator, and a STORE operator. However, it will become evident that this novel invention can be applied to other types of operators as well. At the beginning of the execution of each of the aforementioned operators, information needs to be adjusted to the proper position in the stack of information. For example, at the beginning of an ADD operator, information is stored in both the A register 12 and the B register 14 and if the informa tion is a double word length, then information is also stored in the X register [3 and Y register 15.

The process of adjusting the information in the stack at the beginning of execution of an operator is called the "stack adjust" operation. Assume that an ADD operator is being executed and that none of the registers A, B, X and Y contain information and consider the "stack adjust" operation.

Initially, the control unit causes a word of information to be read from the memory I0 and stored in the B register 14. The control unit 20 senses the tag stored in [4a and if the word is identified as a part of a single precision information unit the word is transferred up to the A register. If, on the other hand, the tag identifies the word in the B register as part of a double precision information unit, the word is transferred over to the Y register 15 and a second word is read out from memory and stored in the B register 14.

Assuming for a moment that the information is a single precision information unit, the word is transferred from the B to the A register, then the control unit 20 causes the next word in memory to be read out and stored in the B register I4. A processing unit senses the single precision tag in 12a and 14a and adds the single precision information words stored in the A and B registers 12 and I4 and stores the result back into the B register I4.

Assume now that the first word stored in the B register 14 is tagged in I40 as being a double precision information unit. The control unit 20 will sense the double precision tag in and will cause the word to be transferred over to the Y register IS. The control unit also causes the second word of the double precision information unit to be read from the memory I0 and stored in the B register 14. Subsequently, the control unit 20 causes the two words stored in the B and Y registers to be transferred up to the A and X registers, respectively. The control unit 20 then causes another word to be read out and stored in the B register 14. The control unit 20 again looks at the tag contained in 12!) and if the word is tagged as a double precision information unit, the word is transferred over to the Y register I5 and the second word of the information unit contained in the memory It) is read out and stored in the B register I4.

An ADD operator is being executed, therefore the control unit 20 senses the double precision tags in I24: and 14a and causes the processing unit 22 to add the content of X and Y together and store the result in the Y register. The control unit 20 then causes the processing unit to add the content of A and 8 together, taking into account any carry out from the Y register and store the result in the B register.

Therefore, it will be evident that the control unit 20 is controlled by the tags contained in the words stored in the A and B registers I2 and I4 and causes the information units to be properly adjusted in the registers and causes the processing unit 22 to process single or double precision information in accordance with the type of information identified by the tags.

When information is read out of memory and stored in the A and B registers it is referred to as adjusting the stack up. Information is also moved from either or both of the A and 8 registers into the memory. This is referred to as adjusting the stack down. Consider the situation where single precision information units are stored in the A and B registers and the stack is to be adjusted down. The control unit 20 senses the single precision tags and the word stored in the B register 14 is stored into memory. Subsequently, the control unit 20 causes the content of the A register 12 to be stored into the B register and then to be stored into memory. Assume now that the stack is to be adjusted down and the information in the A, B, X and Y registers is double precision. The control unit 20 senses the tags and detennines that the information is double precision and then causes the word contained in the B register 14 to be transferred to the memory and subsequently the second word contained in the Y register 15 to be transferred to the memory. In this manner, the double word length information contained in the B and Y registers can be stored in consecutive memory locations of the memory unit 10.

Subsequently, the control unit causes the information contained in the A and X registers to be transferred to the B and Y registers, respectively. Following this transfer the word stored in the B register 14 is stored into memory and then the word contained in the Y register is stored in memory as described above.

It should now be evident that the data processing system is responsive to the tags in the operands for automatically processing a single word or a double word information unit. Additionally, it should be evident that the stack adjusting circuitry is also responsive to the tag bits for automatically transferring a single or a double precision information unit between the registers and the memory as required, independently of the program instruction being executed.

Before giving a detailed description of the circuits, a brief explanation will be given of the symbols and where their meaning can be found. Table I is shown at the end of the detailed description. Table I shows each of the operators which are executed with an explanation of the operation required by the operator. Following Table I is Table II which shows a number of difierent symbols used in the figures along with an explanation of what is represented by each symbol. The symbols shown in Table II represent static conditions in the circuits. Following Table I] is Table III. Table III is a list of action symbols. The action symbols represent certain dynamic operations which take place in the circuits shown in the Figures. Reference should be made to Tables I, II and III to determine the meaning of the symbols used in the figures.

Each of the three operators discussed herein require A, B, X and Y registers to be preloaded in a certain predetermined manner in order for the operator to be executed properly. A decoder 32 shown in FIG. 2 is the operator decoder. Symbols are used to reference the output circuits of the decoder 32 re resentative of each operator. Immediately underneath each of the operator symbols shown at the output of the decoder 32 is the symbol STACK ADJ The two numerals inside of the brackets represent the required condition of the A, B, X and Y registers. The first of the two numerals is indicative of the required condition of the A register (and X register if double precision) and the second numeral is indicative of the required condition of the B register (and the Y register if double precision).

Referring to Table III, it will be noted that the symbol STACK ADJ (l,l) indicates that the stack of information is to be adjusted until both the A and B registers (and the X and Y, if the information is double precision) are full of information. The symbol STACK ADJ (0,2) indicates that the stack is to be adjusted until A register (and the X register, if double precision) is empty but that the B and Y registers are to be disregarded as they can be full or empty. The symbol STACK ADJ (l,2) indicates that the stack isto be adjusted until the A register (and the X register, if double precision) is full, and the content of B and Y registers is to be disregarded. Thus, a "0" in the indicates the corresponding register is to be empty, a l indicates it is to be full and 2" indicates it can be full or empty.

The following discussion is with respect to the circuits of FIG. 3. Certain output circuits are referred to which are not found in FIG. 3. These output circuits are from circuits such as decoders, and flip-flops shown in FIG. 2 which will be discussed in detail hereafter. These outputs are referenced by symbols, which, except for the outputs of the AROF and BROF flip-flops, are shown and explained in Tables I, II and Ill.

Consider now the detailed circuits involved and their operation in carrying out the various STACK ADJ operations. The STACK ADJ operation takes place before an operator is executed. The operation of the computer system for each different STACK ADJ is shown in the flow diagrams of FIGS. 4, 5 and 6. It will be noted that the lower portion of each block in the flow diagram contains a symbol P followed by a numeral. These symbols refer to the output circuits of the control counter 24 shown in FIG. 3 which receive a control signal at that point in the flow. The flow diagrams of FIGS. 4, 5 and 6 should be referred to in the following description of the control circuits of FIG. 3 as they symbolically describe the sequence of the operation of the control counter.

Refer to the control circuits for the STACK ADJ operations which are shown in FIG. 3. Initially the control counter 24 is always in state 0" providing a control signal at P0. The control counter 24 is set to state 0" in response to a control signal at the ADLC. output circuit thereof which receives a control signal after one of the STACK ADJ operations is complete. The control counter 24 has a unique state called the adjust complete state during which the control signal is formed at the ADJ .C. output. When the control counter 24 is in state 0" it can be set to any one of three difi'erent states, namely, state l state 20 or state 40," depending on the particular STACK ADJ operation required for an operator.

First consider the control counter 24 and associated circuits when an ADD operator is decoded requiring a STACK ADJ (l,l) operation. Reference should be made to the flow diagram of FIG. 4 and FIG. 3 in the following discussion. An OR gate 40 and an AND gate 41 are responsive to the coincidence of control signals at the ADD-STACK ADJ (LI) and P0 outputs to set the control counter 24 into state l where a control signal is formed at the Pl output circuit. This initiates the operation for a STACK ADJ (l,l The control counter 24 is also reset into state l when in state 7" if a control signal is formed at B[ 50:3 1:000 output. To be explained in more detail, a control signal is formed at the Bl S0:3]=000 output by the circuits of FIG. 2 when the tag of the word contained in the B register identifies the information as single precision (see Table II). To this end an AND gate 42 is responsive to the coincident of a control signal at P7 and B[50:3 ]=000 to apply a control signal to the OR gate 40 which, in turn, causes the control counter 24 to reset to state I The OR gate 40 also is responsive to a control signal at the P10 output when the counter is in state "10" to cause the counter to be reset to state I When both the AROF and BROF flip-flops are in state "0," a control signal is formed at the output circuit AROBRO of FIG. 2. A control signal at ARO-BRO output causes the control counter 74 to count from state l to state 2."

An AND gate 44 is responsive to the coincidence of control signals at the P2 and BRO output circuits to count the counter from state 2 to state 3 An AND gate 46 sets the counter from state "2" to state 4" in response to the coincidence of control signals at the P2 and BRO output circuits. After the counter is in state "4 it automatically counts to states 5," "6" and 7" in sequences providing control signals at th P5, P6 and P7 output circuits. An AND gate 48 is responsive to the coincidence of control signals at the P7 and B($0:3]==0l0 outputs for setting the control counter from state "7" into state "8." To be explained, the circuits of FIG. 2 apply a control signal at the B[50:3]

=010 output circuit whenever the word contained in the B register is double precision information (see Table 11).

Following state 8" the control counter automatically counts to states 9" and 10" and then back to state l causing control signals at the P9 and P10 output circuits in sequence.

Connected to the control counter 24 is an OR gate 50 which has three AND gates 52, 54 and 56 connected to the input thereof. The OR gate 50 causes the control counter 24 to be set into an adjust complete" state where a control signal is formed at the ADLC. output. This occurs whenever one of the STACK ADJ operations is completed. Referring to the STACK ADJ( 1,1) operation, an AND gate 52 applies a control signal to the OR gate 50 causing the control counter 24 to be set to the adjust complete state in response to a coincidence of control signals at ARO-BRO and PI output circuits.

Once the control counter 24 is in the "adjust complete" state forming a control signal at the ADLC. output, it automatically counts to state "0" where a control signal is formed at the P0 output.

Consider now the circuits and operation involved of the control counter 24 for a STACK ADJ (0,2) operation. An OR gate 58 and an AND gate 59 are responsive to the coincidence of control signals at the LOAD-STACK ADJ (0,2) P.O. outputs for setting the control counter 24 into state 20" where a control signal is formed at the P20 output. This initiates the STACK ADJ (0,2) operation. The OR gate 58 also resets the control counter 24 into state 20" in response to control signals at the P22 and P30 output circuits. Once in state "20" the control counter 24 is set into state 21 and forms a control signal at P21 in response to a control signal at the ARC output.

Referring to FIG. 5, it will be noted that the control counter 24 can either go from state "21 (P21) to either state 22 or state "23" (P22 01' P23). An AND gate 60 is responsive to control signals at P21 and at BRO output circuits for setting the control counter 24 into state 22." An AND gate 62 is responsive to the coincidence of control signals at the P21 and BRO output circuits for setting the control counter 24 into state 23. Once in state "23" the control counter 24 automatically counts to states "24", "25 and "26" forming control signals at the P24, P25 and P26 outputs.

in state 26" the control counter 24 may go either to state "30" or state 27". An AND gate 64 is responsive to the coincidence control signals at P26 and B[50:3 l=0l0 for setting the control counter 24 into state 27" causing a control signal at P27. An OR gate 66 is connected to an AND gate 68. The AND gate 68 causes the OR gate 66 to apply a control signal and set the control counter from state 26" into state 30" in response to the coincidence of control signals at P26 and B[50:3]a=000. The OR gate 66 also causes the control counter 24 to be set to state 30" in response to a control signal at the P29 output circuit.

Returning for a moment to state "27," the control counter 24 is operative for automatically counting to states 28" and 29" following state 27" and, as described hereinabove, the counter is set into state "30" by a control pulse at P29. The control signal at P30 causes the OR gate 50 to reset the counter into state 20" as described hereinabove. When in state 20" and a control signal is formed at the P20 output and at the ARC output, the AND gate 54 causes the gate 50 to set the control counter 24 to the adjust complete" state.

Consider now the STACK ADJ I ,2) operation. This operation takes place at the beginning of the execution of a STORE operator. Reference should be made to the flow diagram of FIG. 6 and the circuit diagram of FIG. 3 during the following discussion. The coincidence of control signals at the STORE- STACK ADJ (1,2) and P0 outputs cause an AND gate 71 and an OR gate 70 to set the control counter 24 from state 0" to state 40" and form a control signal at the P40 output. When in state 40" the control counter can either branch to the adjust complete or go to state 4 l An AND gate '77 is responsive to the coincidence of control signals at the P40 and ARO' outputs for setting the control counter 24 to state 41 The AND gate 56 causes the gate 50 to set the control counter 24 to the "adjust complete state in response to the coincidence of control signals at the P40 and ARO output circuits.

When in state 41" the control counter can either go to state 42" or to state "43. An AND gate 74 is responsive to the control signal at the P41 and BRO outputs for setting the control counter 24 from state 41" to state 42. An AND gate 76 is responsive to the coincidence of control signals at the P41 and BRO outputs for setting the control counter from state "41 to state 43." Once the control counter 24 is in state 43" it automatically counts to states "44," 45," and 46" providing control signals at the P44, P45 and P46 output circuits.

With the control counter in state 46" it can either go to state "47" or to state 50. An AND gate 78 is responsive to the coincidence of control signals at the P46 and B[S0:3]=0l0 outputs for setting the control counter 24 from state 46" into state "47."

An AND gate 80 is responsive to the coincident of control signals at the P46 and B[$0:3]==000 outputs for setting the control counter 24 from state "46" to state "50."

Returning to state 47," once the counter is in state "47 it automatically counts to states 48" and 49" in sequence and then on to state 50" With the structure and operation of the control counter 24 of FIG. 3 in mind, consider the details of and the operation of the circuits shown in MG. 2 while carrying out the STACK ADJ l,l operation for an ADD operator. These circuits are sequenced by and controlled by the control counter of FIG. 3.

The A, B, X and Y registers are shown again in FIG. 2, together with the memory and are referenced by the same symbols as used in FIG. 1. Each of the registers A, B, X and Y have 50 flip-flops referenced by the symbols A] through A50, 81 through B50, X1 through X50 and Y1 through Y50, respectively. Referring to the A register [2, the flip-flops A48, A49 and A50 store the tag bits for the word stored into the A register and are referenced by the symbols 12a. The flip-flops A] through A44 of the A register store the mantissa of a word and are referenced by the symbol l2c. The flip-flops A45, A46 and A47 of the A register store the exponent of the mantissa and are referenced by the symbol 12b. When the tag bits stored in indicate that the word is a single precision word, the exponent in 12b is the exponent of the mantima contained in 120. When the tab bits in 120 indicate that the corresponding information unit is a double precision information unit, the exponent in 121: is the exponent of the mantissa in 120 and of the mantissa stored in the X register 13.

Similar to the A register 12, the B register 14 and X register 13 and Y register l5 have tag flip-flops B48 through B50, X48 through X50 and Y48 through (50, respectively, and are collectively represented by the symbols 14a, 13a and 15a, respectively. Also, similar to the A register, the B, X and Y registers have flip-flops for storing the mantissas of words contained therein, which flip-flops are represented by the symbols Bl through B44, Xl through X44 and Y1 through Y44, respectively, and are collectively represented by the symbols 14c, 13c and 150, respectively. Also similar to the A register, the B register has flipflops for storing the exponents of the mantissas, which flip-flops are represented by the symbols B45, B46, B47. The flip-flops storing the exponent in the B register are collectively represented by the symbol 14b. The flip-flops of the A, B, X and Y flip-flops are conventional flip-flop circuits are well known in the computer art.

The memory 10 is a magnetic core memory having two information registers, 10a and 10b. The information register 10a is the register in which all information being read out of the memory 10 is stored. The information register 10!: is the register in which all information being stored into the memory 10 is stored from the other circuits in the system prior to being written into the memory. Memory 10 is a word oriented memory in which a complete word consisting of 50 bits of information is read out in parallel or written in parallel. The

memory 10 has its own timing and control circuits for causing read and write operations therein. Such read and write control circuits are well known in the computer art.

Associated with the memory 10 is an S register 18. The S register I8 is an address register for the memory 10 which is used for addressing during the stack adjust operations and during reading and writing in the stack.

Associated with the A and B registers are two flip-flops which identify whether the corresponding register is full of information or is empty. The AROF flip-flop is used to mark the A register as full or empty. The BROF flip-flop marks the B register as full or empty. The l state of the AROF and BROF flip-flops indicate the corresponding register is full, whereas the state marks the corresponding register as empty. The output circuits of the AROF and BROF flip-flops which receive a control signal when the corresponding flip-flop is in a l state is represented by symbols ARO and BRO, whereas the output circuits which receive a control signal when the corresponding flip-flops are in a 0" state are represented by the symbols ARO' and BRO.

The memory I0 is shown coupled to an instruction address counter 26 and an S register 18. The instruction address counter 26 addresses the memory .10 causing operators to be read out and stored into an operator register 28. The operator register 28 is the primary register in the system for storing the program operators.

The instruction address counter 26 has gating circuits 30 connected thereto which cause the address contained therein to be counted up by one unit each time a control signal is applied to an operation complete line (0C). To be explained in more detail, the operation complete line (0C) is connected to one of the output circuits of a control counter shown in FIG. 8 which sequences the operation of the system during the execution of the operators stored in the operator register 28.

Although a computer system embodying the present invention may execute many different operators, an explanation is given of the circuits for only executing three operators, namely, an ADD operator, a LOAD operator and a STORE operator. The decoding circuit 32 mentioned above, is connected to the operator register 28 and generates a control signal at one of three output circuits. The three output circuits are referenced by symbols ADD-STACK ADJ (l,I LOAD- STACK ADJ (0,2) and STORE-STACK ADJ (1,2) corresponding to the three different operators being described. The output circuit of the decoder 32 which receives a control signal corresponds to the operator stored in the operator register 28. The output circuits of the decoder are connected to the input of the control counter 24 as discussed above.

Before describing the rest of the circuits of FIG. 2 in detail, consider the operation of the circuits i0, 26, 28, 30 and 32 shown in FIG. 2. A control signal on the operation complete (OC) line causes the gating circuit 30 to count the instruction address counter 26 up one address and causes a gate 34 to couple the incremented address to the memory Ill. The control signal on the operation complete line also applies a control signal to the read input line (R) to the memory causing it to go through a read cycle and read out a stored operator. The operator is stored in the information register 10a. A delay circuit 36 is also responsive to the control signal on the operation complete (OC) line and applies a control signal to a gate 38, after the operator is stored in 100, causing the operator to be stored into the operator register 28. The decoder 32 then decodes the operator and applies a control signal on the appropriate output circuit causing such signal to be applied to the control counter 24.

The memory 10 automatically rewrites the word contained in register 10a back into the same memory location from which it was read in a manner well known in the computer art so as to preserve the information for later use.

Consider the operation of the rest of the circuits of FIG. 2 during the STACK ADJ operations and assume initially that an ADD operator is stored in the ORDER register 28 causing the decoder 32 to form a control signal at the ADD- STACK ADJ (l, I) output as described hereinabove. Reference should be made in the following discussion to the flow diagram of FIG. 4 as well as FIG. 2. The control counter 24 steps from state "0 into state "1 and a control signal is formed at the Pl output. During this time a check is made to see if the A and B registers are full which exists when both the AROF and BROF flip-flops are in a l state causing control signals at both the ARO and BRO outputs. The decoding circuit 82 is coupled to the AROF and BROF flip-flops and provides a control signal at an output AROBRO when both flipflops are in a "I" state and at the output ARO-BRO when either the AROF or the BROF flip-flops are in a "0 state. When both the AROF and BROF flip-flops are in a I state, the STACK ADJ (1,1) operation is complete and the control counter 24 is set into the adjust complete" state forming a control signal at the ADJ.C. output. If, on the other hand, either one or both of the AROF or BROF flip-flops is in a "0" state, then the STACK ADJ (1,1) operation is not complete and the control counter 24 goes on to state 2" forming a control signal at the P2 output.

During state 2" of the control counter 24, a check is made to see if the BROF flip-flop is in a l state, indicating that the B register 14 contains information. Under these conditions a control signal is formed at the BRO output. If the B register is full and a control signal is formed at the BRO output, the counter 24 goes from state 2" to state "3. If, on the other hand, the B register is empty and a control signal is formed at the BRO output, the control counter 24 goes from state 2" to state 4."

Assume now that the B register is full and a control signal is formed at the BRO output causing the control counter to go to state "3." During state 3" the content of the B register is transferred to the A register and the content of the Y register is transferred to the X register. In this manner, information contained in the stack in the B register is moved from the B register and Y register up to the A register and the X register. If the information happens to be single precision information then the information transferred from Y to X is disregarded. If, on the other hand, the information is double precision then the information transferred from the Y register to the X register is significant and will be used in the subsequent ADD operation. Also during state 3, the AROF flipflop is set to state I" to indicate that the A register is now full and the BROF flip-flop is set to a 0" state indicating that the B register is now empty.

Consider the circuits shown in FIG. 2 for effecting the above-described operation during state 3. A gating circuit 84 is coupled between the output of the B register 14 and the input of the A register 12. An OR gate 86 is responsive to a control signal at the P3 output for causing the gate 84 to store the content of the B register 14 into the A register 12. Corresponding to the gate 84, a gate 88 is coupled between the Y and X registers and is controlled by an OR gate 90. Similarly, the OR gate 90 is responsive to the control signal at P3 for causing the gate 88 to store the content of the Y register into the X register. Referring to the AROF and BROF flip-flops, an OR gate 92 is coupled to the input of the AROF flip-flop which sets it into a l state. The OR gate 92 is responsive to a control signal at F3 for setting the AROF flip-flop to a I state. Also, an OR gate 94 is connected to the input of the BROF flip-flop which sets it into a 0" state. A control signal at P3 causes the OR gate 94 to set the BROF flip-flop into a 0" state.

At the end of state 3," the control counter 24 goes to states "4" and 5" fanning control signals at the P4 and P5 outputs. During the states 4" and "5 the word in the stack of infor mation contained in the memory 10 is read out and stored into the B register and the BROF flip-flop is set to a I state, indicating the B register is full. To this end, an OR gate 96 is responsive to a control signal at P4 to apply a control signal to the read input (R) of the memory 10 and to apply a control signal through the OR gate 98 to a gate 100. This causes the gate 100 to gate the address contained in the S register 18 to the memory 10 and causes the addressed memory location to be read out and stored into the information register I00. The S register I8 always points to the top of the stack in memory, therefore, the top word of the stack in memory is read.

Also, the control signal at P4 causes a gate 102 to set the BROF flip-flop to a l state. The control pulse at P5 causes an OR gate 106 to apply a control signal to a gate 104. The gate I04 is responsive to this control signal to store the word contained in the information register I into the B register I4.

At the end of state 5," the control counter 24 goes to state 6" where the content of the S register I8 is counted down by one address to point at the next word of information in the corresponding stack. To this end, an OR gate I08 is responsive to the control signal at P6 to cause a count control circuit 110 to count the address contained in the S register 18 down by one address.

Following state "6," the control counter 24 goes to state "7" and forms a control signal at P7. During state 7" the content of the B register is checked to whether or not it contains a word ofa double precision information unit (BI 50:3]=0l0). If the word is a double precision information unit, then the control counter 24 goes to state 8." If, on the other hand, the word contained in the B register is part of a single precision information unit (B(50:3]#)00), the counter is reset back to state A decoding circuit I12 is coupled to the tag flipflops 12a and I40 of the A register and B register. The decoding circuit I12 forms a control signal at the B[50:3]=0l0 output whenever the word contained in the B register is part of a double precision word and at the B[50:3]=000 output when part of a single precision information unit. Thus, a control signal at B[50:3 ]=0l0 (double precision) causes the control unit 24 to go from state "7 to state 8" whereas a control signal at B[ 50:3]=000 causes it to go back to state 1."

Assume that a double precision word is contained in the B register and hence a second word needs to be read from the stack in the memory. Information is arranged in the memory so that the least significant word of a double precision information unit is read from memory first, followed by the most significant word. Therefore, assuming a double precision information unit is being handled the B register now contains the least significant word thereof and must be transferred to the Y register.

During states 8" and "9," the content of the B register is transferred to the Y register and the next word in the stack is read from the memory and stored in the B register. To this end, a gate I14 stores the content of the B register into the Y register in response to a control signal from an OR gate I16. The OR gate I16 applies a control signal to the gate II4 in response to the control signal at P8. Initially the control signal at P8 also causes the OR gate 96 to apply a control signal to the read (R) input of the memory 10 and to the OR gate 98 which in turn applies a control signal to the gate 100. This causes the decremented address contained in the S register 18 to be used to address the memory I0 and causes the content of the addressed memory location to be read out to the information register I00. The control counter goes to state "9" and the control pulse at P9 causes the OR gate 106 to cause the gate 104 to store the word contained in the information register 100 into the B register I4. Thus, at the end of state 9," the least significant word of a double precision information unit is stored in the Y register I and the most significant word is stored in the B register 14.

At the end of state 9" the control counter 24 goes to state l0" and the control signal at Pll] causes the gate I08 to again activate the count control circuit IIO which in turn counts the address contained in the S register I8 down one unit. At the end of state the control unit 24 goes back to state l Once the control counter 24 is back in state "I it will continue on through states "2" through "l0" again or will go to an adjust complete" state where a control signal is formed at the AD.I.C. output. The adjust complete" state is only entered when both the A register and the B register are full as indicated by control signals at the output circuit ARO-BRO from the decoder 82. States 2" through "ID" are entered again if initially the B register is empty.

It should now be evident that the ADD operator causes a stack adjust operation to take place without specifying whether the corresponding information is single or double precision. The circuits of FIGS. 2 and 3 automatically shift the information from the B register to the A register and causes information to be read from the memory I0 and stored into the B register I4 for single precision information. If, however, the decoder circuit I12 detects that the information is double precision, it causes the control counter 24 to enter states "8, "9" and 10" where another word is read from the memory and stored in the B register while the former information is transferred from the B register to the Y register. Therefore, the transfer gates and control circuits automatically handle the information in accordance with single precision or double precision, depending on the tags of the words stored in the B register.

Consider now the STACK ADJ 0,2) operation which occurs at the beginning of execution of a LOAD operator. Assume initially that a LOAD operator has been read from the memory I0 and stored in the operator register 28 causing a control signal at the LOAD-STACK ADJ( 0,2) output. During the following discussion reference should be made to the flow diagram of FIG. 5 and the circuit diagram of FIG. 2.

The control signal at the LOAD-STACK ADJ (0,2) output causes the control counter 24 to enter state 20" where a check is made to see whether the A register is empty. If the A register is empty a control signal is formed at the ARO' output of the AROF flip-flop. When the A register is empty the STACK ADJ (0,2) operation is complete regardless of the condition of the B register. The reason being that STACK ADJ (0,2) indicates that any information contained in the A register is to be moved out thereof. Stating it differently, the stack needs to be adjusted down so that the A register is empty.

If the A register is full the AROF flip-flop is in a l state causing a control signal at the ARO output. This causes the control counter 24 to go from state 20" to state 21." During state 2 I the B register is checked to see whether it is empty BRO). If the B register is empty then state 22" is entered where the content of the A register is stored in the B register, the content of the X register is stored in the Y register, the AROF flip-flop is set to a "0" state to mark that it is empty and the BROF flip-flop is set to a I state indicating that the B register is full.

Consider now the operation of the circuits shown in FIG. 2 during state 22. The control signal at P22 causes an OR gate I20 to activate a gate 122 causing it to store the content of the A register into the B register. Corresponding to the gates I20 and 122 are an OR gate I24 and a gate I27. The OR gate 124 causes the gate 127 to store the content of the X register into the Y register in response to the control signal at P22. The OR gate 126 is responsive to the control signal at P22 for resetting the AROF flip-flop into a 0" state. An OR gate 102 is responsive to the control signal at P22 for setting the BROF flip-flop into a I "state.

Following state 22" the control counter 24 is set back to state 20" and at this point the A register is empty and a control signal is formed at the ARC output. This causes the control counter 24 to enter the "adjust complete" state and form a control signal at the AD.I.C. output, causing the STACK ADJ (0,2) operation to be terminated.

Assume now that during state "2|" of the control counter 24 it is found that the B register is full. A control signal being formed at the BRO output. This will cause the control counter 24 to go to state 23 urirtg state 23 the content of the S register [0 is counted up by one address. To this end, an OR gate I29 is responsive to the control signal at P23 to cause a count control circuit I28 to count the address contained in the S register 18 up one address.

Subsequently, the control counter 24 goes to states "24" and 25" during which the content of the B register is stored into the memory 10 and the BROF flip-flop is set to a state thereby marking the B register as empty.

Consider now the operation during states 24" and "25. The control signal at the P24 output causes a gate 130 to store the content of the B register into the information register b, and causes the OR gate 94 to reset the BROF flip-flop to a 0" state. The control signal at P25 causes an OR" gate 132 to apply a control signal to the write (W) input of the memory 10 and to the OR gate 98. The OR gate 98 in turn causes the gate 100 to couple the address contained in the S address register to the memory 10 and the information contained in the information register 10!) is written into the addressed location.

Following state 2S, the control counter 24 goes to state 26 where the circuits check to see whether or not the tag bits in the B register designate the information as double precision. If the tag bits in section 140 of the B register indicate that the information which has just been stored in the memory is double precision (B[ 50:3 }=0IO), then state "27" is entered. If on the other hand, the tag bits indicate that the information is single precision (B[50:3]=000), then the control counter 24 skips from state 26" to state 303' Assume that the information that was just stored in the memory 10 is part of a double precision information unit and hence a word is contained in the I register that needs to be stored into memory. The control signal at P27 causes the gate 129 to activate the count control circuit 128 which, in turn, counts the address contained in the S register 18 up one address. Thus, the S register 18 now points at an empty memory location. Subsequently, the control counter 24 goes to state "28 and then to state 29." The control pulse at P28 causes a gate 134 to store the content of the Y register into the information register 10b and the control signal at P29 causes the OR gate 132 to apply another control signal to the write (W) input of the memory 10 and to the OR gate 98. The OR gate 98 in turn causes the gate 100 to couple the incremented address from the S register to the memory. The memory then writes the word in the information register 106 (from the Y register) into the addressed memory location.

Subsequently the control counter 24 goes to state 30. During state 30" the content of the A register is transferred to the B register, the content of the X register is transferred to the Y register, the AROF flip-flop is set to a 0" state marking the A register as empty and the BROF flip-flop is set to a I state marking the B register as being full. To this end the control signal at P30 causes the gates 120, 122 and 124, 126 to store the content of the A and X registers into the B and Y reg|sters and cause the OR gate 126 and the OR gate 102 to set the AROF and BROF flip-flops into states "0" and 1," respectively, similar to that described above.

The control counter 24 now returns to state 20" and then goes to the adjust complete" state terminating the STACK ADJ (0,2) operation.

It can now be seen that the STACK ADJ (0,2) operation and corresponding circuitry respond to the tag bits contained in the B register 14 and causes the information to be handled as single or double precision, depending on the tag bits. Thus, the LOAD operator specifies that the information is to be adjusted in a certain manner in the A and B registers and the transfer circuitry and control circuitry described hereinabove automatically, in response to the tag bits, adjust the informatron as single or double precision, depending on the particular type of information.

The sequence of steps of the system shown in FIG. 2 during STACK ADJ (1,2) operation is shown in the flow diagram of FIG. 6. The STACK ADJ l,2) operation takes place at the beginning of execution of a STORE operator. The operation of the system for a STACK ADJ (1,2) is such that the stack of information is adjusted so that the A register (and the X register, it double precision) is filled without regard to the content ol'the B register. The operation for a STACK ADJ 1,2) is easily understood with reference to the flow diagram of FIG. 6

and the explanation of symbols in Tables I, II, and III in the same manner as that described hereinabove for FIGS. 4 and 5 and will not be given in detail as was done for FIGS. 4 and 5.

Refer now to FIG. 7 which is a block diagram showing the circuits for execution of the ADD, LOAD and STORE operators. A number of the circuits shown in FIG. 2 are repeated again in FIG. 7 and common reference numerals are used therefor. In order to simplify the block diagram of FIG. 7, certain of the circuits essential for the execution of operators shown in FIG. 2 are not shown again in FIG. 7. For example, the instruction address counter 26, gate 34, control circuits 30, delay circuit 36, gate 38 order register 28 and decoder 32 are essential for obtaining, storing and decoding the operators. To be explained in more detail, the output of the decoder 32 is used at the appropriate places in the control unit shown in FIG. 8 which controls the operation of the circuits shown in FIG. 7.

Before considering the block diagram of FIG. 7 in detail, refer to the control circuits of FIG. 8 which control the operation of the system shown in FIG. 7 while executing ADD, LOAD and STORE operators. The control circuits of FIG. 8 are part of the control unit 20 shown in FIG. I. Included therein is a control counter 140. The control counter has a number of different states during which control signals are formed at the indicated output circuits. All of the outputs except one are referenced by the symbol T" followed by a numeral that corresponds to the state of the counter 140 causing the control signal thereat. One output is represented by the symbol 0.C. and receives a control signal when the counter 140 is in a unique state referred to as the operation complete" state. The flow diagrams of FIGS. 9, 10 and 11 illustrate the sequence of operation of the control counter 140 as well as the operation of the circuits shown in FIG. 7.

It will be noted that some of the inputs to the circuits of FIG. 7 are from output circuits which are not shown in FIG. 7. These output circuits and the circuits to which they are connected are shown in FIGS. 2, 3 and 6 and will be referred to in connection with the operation of the circuits of FIG. 7. Refer now to the circuits of FIG. 7 for causing an ADD operator to be executed and to the flow diagram of FIG. 9 which symbolically describes the operation. Initially, the control counter [40 is in state 0" and forms a control signal at the output T0. The control signal at the ADD-STACK ADJ (l,l output in combination with a control signal at the ADIC. output of the control counter 24 (see FIG. 3) causes an AND gate 142 to set the control counter 140 into state 0' (to be distinguished from state 0). The control counter 140 is set from state "0" to one of two different states, namely, states l or "10." If TO'information being operated on is single precision the control counter goes to state I and if the double precision, to state 10." T0

The coincidence of control signals at the output circuits T0 and A [50:3]-B[50:3]=000 cause the control counter 140 to be set from state 0' into state l." The coincidence of control signals at the output circuits T0 and A[50:3]+B[50:3 ]=0l0 causes an AND gate 144 to set the control counter 140 from state 0' to state l0."

Returning to state "1," the control counter 140 can go from state 1" to any one of states "2," 3, 4" or operation comelete" (O.C.). A control signal at the output circuit A W BML (from FIG. 2) causes an OR gate 148 to apply a control signal to an AND gate 146. The AND gate 146 is responsive to such control signal in coincidence with the control signal at T1 to apply a signal through an OR gate to the control counter 140 setting it into state An AND gate 150 is responsive to the coincidence of control signals at the output circuits T1 and WAML'WBML for setting the control counter 140 to state 3." An AND gate 152 is responsive to the coincidence of control signals at T1 and WAML-WBML for setting the control counter 140 from state I to state "4.

An OR gate 154 is provided to set the control counter 140 into the operation complete" state wherein a control signal is formed at the QC. output. The OR gate 154 has an input connected to the output of an AND gate 156. The coincidence of control signals at the output circuits TI and WWBML cause the AND gate I56 to apply a control signal through the OR gate I54 to the control counter I40 causing it to be set from state l to the operation complete" state. The control counter I40 is operative for automatically going from the operation complete" state back to state "0."

Once the control counter I40 is in state "2, the control signal at the T2 output causes the OR gate I54 to set it to the operation complete" state.

Consider now state 3" of the control counter I40. Once the control counter I40 is in state 3, it automatically goes to state 6. To this end, an OR gate I62 is responsive to a control signal at the T3 output for setting the control counter 140 from state "3" to state 6."

Consider now state 4. When in state 4, the control counter 140 may either go directly to state 6" or to state and then to state "6." An AND gate 158 is responsive to a control signal at the T4 output in coincidence with a control signal at the Eu 7* Eb output for setting the control counter to state S. Once in state "5, the coincidence of control signals at the T5 and Err-Eb outputs cause an AND gate 160 to apply a control signal through the OR gate I61 to the control counter, setting it from state "5 to state 6."

Refer again back to state "4." An AND gate I64 is responsive to the coincidence of control signals at the T4 and Ea-Eb output for applying a control signal through the OR gate 162 to the control counter I40 setting it from state "4 to state Once the control counter 140 is in state 6," it automatically goes to the operation complete" state. To this end, the OR gate I54 is responsive to the control signal at T6 for setting the counter into the "operation complete" state.

It should be noted that the operation of the control counter 140 up to this point for states l to 6" has been for single precision information. The operation of the control counter I40 for states 10" through 16" is for double precision information. The control counter is set from state "0" to state 10" under control of the AND gate I44 as described hereinabove. Once in state 10" the control counter automatically counts to state I 1.

During state 1 l" the control counter 140 goes to any one of four different states. An AND gate I66 is responsive to the coincidence of control signals at the TH and ADML'BDML output circuits for setting the control counter I40 from state I l" to state l2. An AND gate I68 is responsive to the coincidence of control signals at the TI] and ADML'BDMI: for setting the control counter 140 into state l4." An AND gate 174 is res onsive to the coincidence of control signals at the T11 and AD L-BDML output circuit for applying a signal through the OR gate 154 for setting the control counter 140 into the operation complete"state.

An AND gating circuit I47 is responsive to a control signal at TM in coincidence with a control signal at the outputs for applying a control signal through the OR gate I45 and resetting the control counter to state Once the control counter is in state l 2" it can either go to state "13 or to state 153' An AND gate I67 is responsive to the coincidence of control signals at the T12 and Ea #Eh outputs for setting the control counter I40 into state "l3." An AND gate I72 is responsive to the coincidence of control signals at the T12 and at Ea=Eb outputs for applying a control signal through the gate I70 setting the control counter I40 into state l5." The OR gate I70 is responsive to the coincidence of controi signals at T13 and T14 for setting the control counter from states "13 and l 4," respectively, [0 state l5."Once the control counter is in state "l5 it automatically counts to state "16. The OR gate I54 is responsive to a control signal at T16 for setting the control counter to the "operation complete state.

Consider now the portion of the control counter shown in FIG. 8 for causing a LOAD operator to be executed. During the following discussion, reference should be made to FIGS. 8 and 10, FIG. I0 showing a flow diagram for execution of a LOAD operator.

An AND gate 175 is responsive to the coincidence of control signals at the LOAD-STACK ADJ (0,2) and ADJ.C. output for setting the control counter I40 into state 20." Once the control counter I40 is in state 20" it automatically counts to state 21 and then on to state 22."

Once the control counter I40 is in state 22" it either goes to state 23" or to state "26. An AND gate I76 is responsive to the coincidence of a control signal at the T22 and A[50:3] -0l0 outputs for setting the control counter 140 into state 23."An AND gate I is responsive to the coincidence of control signals at the T22 and A[S0:3 P000 outputs for applying a control signal through an OR gate 178 to the control counter setting it to state 26." The control counter, once in state "23," automatically counts to states 24" and 253' The OR gate 178 is responsive to a control signal at the T25 output for setting the control counter 140 to state "26." The OR gate I54 is responsive to the control signal at T26 for setting the counter from state 26" to the operation complete" state.

Consider now the portion of the control counter 140 of FIG. 8 which pertains to the STORE operator. Reference should be made during the following discussion to the STORE flow of FIG. II and the circuits of FIG. 8.

The control counter 140 is set from state "0" to state 30" by an AND gate I82. The AND gate 182 sets the control counter into state 30" in response to the coincidence of control signals at the output circuits STORE-STACK ADJ (1,2) and AD.I.C. Once in state 30," the control counter I40 counts to states3 l 32, "33."

Once the control counter I40 is in state 33, it either goes to state 34" or to state 38."

An AND gate I84 is responsive to the coincidence of control signals at the T33 and A[50:3]-B[50:3] outputs for setting the control counter 140 into state 34. An OR gate is responsive to the coincidence of signals at T33 and A[50:3]#B[ 50:3l for setting the control counter into state .Qnsst aqntrplscsnts s stateffi iitssn e ther 59 o state 35" or to the operation complete (O.C.) state. An AND gate I86 is responsive to the coincidence of control signals at the T34 and B[50:3]=0l0 outputs for setting the control counter I40 into state 35." Once in state 35" the control counter counts to states 35," 36,"and 37."

The gate 154 is responsive to a control signal at T37 for setting the control counter from state 37" to the operation complete"state.

An AND gate I83 is responsive to the coincidence of control signals at the T34 and B[50:3]=000 outputs for applying a control signal through the OR gate 154 to the control counter 140 setting it into the "operation complete" (O.C.) state.

Assuming the control counter has been set to state "38" it is set to one of states 39" and 40" An AND gate 187 sets the control counter from state "38" to state 39" in response to the coincidence of control signals at T38 and B[50:3]-0l0. An AND gate I89 sets the control counter from state "38" to state 40" in response to the coincidence of control signals at T38 and B[50:3 ]=-000.

The control counter I40 automatically counts from states 37" and 40" to state 4l." Once in state "41" the control counter I40 automatically counts to state 42" and back to state .33."

With the portion of the control unit shown in FIG. 8, in mind, consider the operation of the system shown in FIG. 7 which the control unit I40 sequences.

F irst. the operation of the computer system shown in FIG. 7 during the exec ution of an ADD operation will be described. During the following discussion reference should be made to the ADD flow diagram of FIG. 9 and the block diagram of FIG. 7.

Initially an ADD operator is read out from the memory and stored into the ORDER register 28 (see FIG. 2). A decoder 32 decodes the ADD operator and provides a control signal at the ADD-STACK ADJ (1,1) output. Initially the stack is adjusted so that both the A and B registers are full in accordance with the ADJ .STACK (l,l) operation described hereinabove. When the stack has been adjusted, a control signal is formed at the ADJ.C. output as described hereinabove causing the control counter I40 to go from state 0" to state 0'."

Assume for the following discussion that the tag bits of the words contained in the A and B registers identify the corresponding words as part of a single precision information unit. During state 0' a check is made to see if the information is single precision. If both words are single precision a control signal is formed at the A[ 50:3} B[50:3}=000 output of the decoder I12 causing the control counter to go from state "0'" to state l." The decoder I12 is shown in FIG. 7 and is the same decoder as is shown in FIG. 2 but with additional Outputs pertinent to FIG. 7.

During state "I" a check is made to see if the mantissas of the words contained in the A and B registers are equal to zero and the AROF flip-flop is set to a "0" state to mark the A register as being empty. The A register is marked as being empty because during the subsequent states of the control counter I40 the contents of the A and B registers are combined and the results stored in the B register so that the content in the A register can be disregarded thereafter. To this end, the OR gate I26 (the same as the OR gate 126 of FIG. 2), is responsive to the control signal at T1 for setting the AROF flip-flop to a0" state.

The control counter 140 branches from state 1'' into one of four different states. The state into which the control counter goes is dependent on the value of the mantissas in the A and B registers. A decoding circuit I92 is coupled to the mantissa sections 12c and Me of the A and B registers. If the mantissas contained in the A and B reg'sters are both zero, the decodin circuit 192 fonns a control signal at the WAML- BML output and the control counter 140 branches to state "2." Since both mantissas are zero, the exponent contained in the B register is to be cleared to zero to reflect the zero value of the result. Also, the mantissa and exponent in sections c and 15b of the Y register are cleared to zero. The clearing of the Y register to zero is only of significance when handling double precision information, and not when handling single precision information. During the foregoing operation, a gate 194 is responsive to the control signal at T2 for setting the exponent and mantissa sections [4b and I41: and 15b and 15c of the B and Y registers to zero. Subsequently, the control counter 140 goes into the operation complete" state forming a control signal at the DC. output.

Assume now that the control unit I40 is back into state l and this time that the mantissa in the A register is zero but that the mantissa of the B register contains information and is not zero. This means that the operation of the system of FIG. 7 is complete and execution of the ADD operator is terminated. To this end, the decoder I92 forms a control signal at the WAHEW BML output indicating that the A register is empty, whereas the B register contains information. This causes the control counter 140 to be set into the "operation complete" state and terminate the execution of the ADD operator.

Assume now that the control unit is back in state l again and this time that the A register contains information, whereas the B register contains a zero mantissa. The decoder 192 fonns a control sigtal at the WAML-WBML output causing the control counter to go from state I to state "3."

Since the mantissa in the B register is zero, whereas a nonzero mantissa is contained in the A register, the exponent of the word contained in the B register can be disregarded and the mantissa contained in the A register is transferred directly to the B register for use in making up the result of the addition. To this end, the exponent contained in 12b of the A register is transferred to [4b of the B register (B[45:3]-A[4$:3]). To this end, an OR gate I96 is responsive to the control signal at T3 for applying a control signal to a gate I98 causing it to store the exponent contained in 12b of the A register to 14b of the B register.

The control unit then goes from state 3" to state 6 where the mantissas contained in the A and B registers are added together and the result stored in 14c of the B register. A conventional full adder circuit 200 is provided for adding the mantissa contained in the A register to the mantissa contained in the B register. The adder 200 adds the mantissa of the A and B registers in parallel and provides a parallel output corresponding to the result. The signal at T6 causes an OR gate 202 to activate a gate 204 which couples the output of the mantissa sections and Me of the A nd B registers to the input of the adder 200. This causes the adder to add the content of 12c to I40 and provide an output corresponding to the sum. The OR gate 202 also applies a control signal to a gate 206 causing it to store the sum formed at the output of the adder 200 back into the mantissa section of the B register.

Following state "6" the control counter I40 goes to the "operation complete" state where the ADD operation is complete, leaving the sum in the B register.

Return now to state l of the control counter 140 and as surne this time that the mantissas of the words in the A and B registers are both nonzero. The decoder 192 forms the control signal at the WAML-WBML output indicating that both mantissas are nonzero. This causes the control counter 140 to go from state l to state 4.

During state 4" a check is made to see if the exponents of the two words contained in the A and B registers are equal. A compare circuit 208 is provided for comparing the exponents contained in 12b and 14b of the A and B register. The compare circuit 208 forms a control signal at the output circuits Ba -Eh and Ear Eb outputs whenever the exponents are equal and not equal, respectively. Assume that the exponents are equal and that the compare circuit 208 forms a control signal at the output EFEb during state 43' This causes the control counter 110 to go from state 4" to state 6" where the mantisms of the words contained in the A and B registers are added together as described hereinabove and the result is stored in the B register.

Assume that in state "4" the compare circuit 208 detects the exponents are not equal and the control signal is formed at th Ed at Eb qtm tl is s sss h FPHIFQI vs me M m 59 p from state P' to state 5".

During state 5" the position of the mantissas contained in the A and B registers are adjusted while the value of the ex ponents are modified by a corresponding amount until the exponents of the words contained in the A and B registers are equal. A conventional normalizing logic circuit 210 is provided for this purpose. Normalizing logic is well known in the computer art. One example of such logic is described in US. Pat. No. 3,244,864, assigned to the same assignee as the present application. The normalizing logic 210 causes the mantissa contained in the A and B registers to be shifted relative to each other automatically and the exponents modified by a corresponding amount until the exponents are equal. The normalizing logic and control circuit 210 is responsive to a controi pulse at the T5 output for normalizing the words contained in the A and B registers.

Assume now that the mantissa: of the two words are normalized and the exponents are equal and the compare circuit 208 forms a control signal at the Bm=Eb output so indicating. This causes the control counter 140 to go from state 5" to state "6" where the two mantissa: are added together and the result stored in the B register as described hereinabove.

Thus, the computer system of FIGS. '7 and B is responsive to a conventional add command, which does not specify whether the operand information is single or double precision. The operand words themselves contained in the A and B registers contain tag bits which identify the corresponding information unit as single or double precision. When the information is detected as single precision the system automatically goes from state 0" to states "I through 6" where the information is handled as single precision information. 

1. In a data processing apparatus the combination comprising, register means for storing a first word and an extension word of the same information unit for processing, said information unit having as a part thereof a tag which identifies whether the corresponding information unit contains an extension word, means for processing a word stored in said register means and including means responsive to said tag in an information unit identifying an extension word for automatically processing the extension word thereof together with the first word and thereby form a result having a double word length.
 2. In a data processing apparatus as defined in claim 1 wherein said information unit contains said tag in the first word and wherein said register means comprises a first register for storing a first word for processing and an extension register for storing an extension word for processing, decoding means coupled to said first register for providing a predetermined signal when the tag therein identifies an extension word, said processing means being responsive to said predetermined signal for processing the word stored in said extension register.
 3. In a data processing apparatus as defined in claim 2 wherein said processing means comprises an adder and gating means for coupling a word contained in said extension register means to said adder in response to said predetermined signal.
 4. In a data processing apparatus for processing information of a single or a double word length, the combination comprising, a register for storing a first word for processing, an extension register for said register in which an extension of said first word may be stored for processing, said first word having a tag which identifies whether the corresponding information is a single word or is a double word having an extension word, storage means for storing an operator identifying an operation to be performed on said first word, means for processing the first word in said register in accordance with a stored operator, said processing means including means responsive to the tag in the word being processed indicating that an extension word is stored in the extension register for automatically processing sucH extension word together with the first word and thereby form a result having a double word length.
 5. In a data processing apparatus for processing information units of a single or a double word length, the combination comprising, first and second registers for storing first and second words of an information unit for processing, an extension register for each of said registers in which an extension of each of said words may be stored for processing, each of said first and second words having a tag which identifies whether the corresponding information unit is a single word or is a double word having an extension word, storage means for storing an operator identifying an operation to be performed on said first and second words, means for processing the content of said first and second registers in accordance with a stored operator, said processing means including means responsive to the tag in one or the other or both of said first and second registers indicating the an extension word is stored in the corresponding register for automatically processing such extension word which in present together with the first and second words and thereby form a result having a double word length.
 6. In a data processing apparatus as defined in claim 5 including detection means coupled to said first and second register means for detecting a tag identifying a double word, said processing means comprising gating means for coupling the words in said first and second registers to said processing means and for storing the result formed by the processing means into the second register, said gating means additionally being responsive to such detection for coupling the extension words in said extension registers to said processing means and for storing the result formed by said processing means into the extension register for said second register and thereby cause a double word length result to be stored in the second register and the corresponding extension register.
 7. In a data processing apparatus for storing into memory, the combination comprising register means for storing a first word and an extension word forming an information unit, said information unit having a tag which identifies an extended word length information unit, memory means for storing information units from said register means, word by word an means operative for transferring a single word from said register means to said memory means and operative in response to said tag in an information unit identifying an extended word length for transferring an extension word from said register means to said memory means and thereby cause an extended information unit to be stored into the memory means.
 8. In a data processing apparatus as defined in claim 7 including an operator register for storing operators for execution, said means for transferring being operative in response to a store operator for transferring a single word from said register means to said memory means for storage, said transfer means including means additionally responsive to said tag in an information unit stored in said register means for additionally transferring such extension word to the memory means for storage.
 9. In a data processing apparatus for storing into a memory information unit of single or double word lengths, the combination comprising a first register for storing a word, an extension register for storing an extension of said word, said first word having a tag which identifies whether the corresponding information unit is of a single or a double word length, memory means, means for detecting a tag in said first register indicating a double word length information unit, means operative for only storing a single word from said first register into said memory in the absence of a detection by said detection means and operative in response to such detection for additionally storing a word contained in said extension register into said memory means and thereby cause a double word information unit to be stored into the memory means.
 10. In a data processing apparatus for loading into registers for processing information units of single or double lengths, the combination comprising a first register for storing a word, an extension register for storing an extension of said word, said word having a tag which identifies whether the corresponding information unit is of a single or a double word length, memory means for storing words and extension words, means for reading out a word from said memory means and including means for storing such word in the first register means, means for detecting a tag in said first register indicating a double word length information unit, said reading means additionally being operative in response to said detection by said detection means for reading out a second word from said memory means and for storing the same in said extension register and thereby cause automatic storing of a double length information unit.
 11. In a data processing apparatus, the combination comprising register means for storing an information unit, memory means, said register means having a register for storing a word for processing and a second register for storing a second word when the information unit is of a double word length, an information unit in said register means having a tag as a part thereof which identifies it as single or double word length information, and means for transferring a word of an information unit between the memory means and said register means and responsive to a tag in such word indicating double word length information for automatically transferring a second word therebetween.
 12. In a data processing system as defined in claim 11 including means coupled to said first and second register means for detecting a tag therein indicating a double word length information unit and for providing a signal to said transfer means causing the transfer of double word length information.
 13. In a data processing system as defined in claim 11 including means responsive to an operator stored in said operator register means for providing a unique signal to said transfer means indicative of a required transfer between each register means and the memory means and thereby cause the transfer means to selectively transfer at least a single word between said register means and said memory means and means responsive to a tag contained in an information unit stored in said register means indicating double word length information for applying a signal to said transfer means causing a second word to be transferred between said register means and said memory means.
 14. In a data processing apparatus for processing information of a single or a double word length in a stack of information, the combination comprising first and second register means for storing the top two information units of a stack of information, memory means for storing the rest of the information units of such stack, each of said register means having a register for storing a word for processing and a second register for storing a second word when the corresponding information unit is of a double word length, an information unit stored in said first and second register means having a tag as a part thereof which identifies it as single or double word length, processing means for the information stored in said first and second register means, register means for storing an operator for controlling the operation of said processing means, and stack adjust means for transferring a word of an information unit between the memory means and said register means and responsive to a tag bit in the information unit indicating double word length information for automatically transferring a second word therebetween.
 15. In a data processing apparatus for processing information of a single or a double word length in a stack of information, the combination comprising first and second register means for storing the top two information units of a stack of information, memory means for storing the rest of the information units Of such stack, each of said register means having a register for storing a word for processing and a second register for storing a second word when the information unit is of a double word length, a word stored in said first and second register means having a tag as a part thereof which identifies it as part of single or double word length information, processing means for the information stored in said first and second register means, register means for storing an operator for controlling the operation of said processing means, and stack adjust means for transferring information between said register means and the memory means comprising means for reading a word from said memory means and for storing such word in one of said register means, means for detecting a tag in the stored word indicating double word length information, and means responsive to such detection for reading a second word from said memory means and for storing such second word in the same register means thereby forming double word length information therein.
 16. In a data processing apparatus for processing information of a single or a double word length in a stack of information, the combination comprising first and second register means forming the top two information units of a stack of information, memory means for storing the rest of the information units of such stack, each of said register means having a register for storing a word for processing and a second register for storing a second word when the information unit is of a double word length, a word stored in said first and second register means having a tag as a part thereof which identifies it as part of single or double word length information; processing means for the information stored in said first and second register means; register means for storing an operator for controlling the operation of said processing means, and stack adjust means for transferring information between said register means and said memory means comprising means for transferring a word from one of said register means to said memory means, means for detecting a tag bit in such word indicating double word length information, and means responsive to such detection for automatically transferring a second word from the same register means to said memory means and thereby cause double word length information to be stored.
 17. In a data processing apparatus for processing information of a single or a double word length in a stack of information the combination comprising first and second register means forming the top two information units of a stack of information; memory means for storing the rest of the information units of such stack, each of said register means having a register for storing a word for processing and a second register for storing a second word when the information unit is of a double word length, a word stored in said first and second register means having a tag as a part thereof which identifies it as part of single or double word length information, processing means for the information stored in said first and second register means; register means for storing an operator for controlling the operation of said processing means; and stack adjust means selectively responsive to an operator for transferring information between said register means and said memory means comprising means for transferring a word contained in a register of said register means to said memory means, means for detecting a tag in such word indicating double word length information, and means responsive to such detection for transferring a second word from the other register in such register means to said memory means for storage and thereby automatically effect the storage of double word length information.
 18. In a data processing apparatus for processing information of a single or a double word length in a stack of information arranged on a last in, first out, basis the combination comprising memory means for storing information in stacks, counting means for automaticalLy providing an indication of the memory location containing the top of a stack of information in said memory means, first and second registers external to said memory means for storing the first and second words in the top of the stack, each of said words in the stack having a tag which identifies whether the corresponding word is a single or is a double word; an extension register for each of said first and second registers for storing a second word of double word length information, register means for storing operators, means for automatically moving information between said first and second registers and the stack in said memory means as specified for a particular stored operator including means for detecting a tag in a word stored in said first and second registers and for providing an indication of double word length information, and transfer means responsive to said indication for automatically transferring another word between the memory location of said memory means indicated by said counting means and the corresponding extension register and thereby cause double word length information to be transferred.
 19. In a data processing system, the apparatus comprising: a memory having a plurality of addressable locations for storing information units, each information unit comprising at least one word having an associated tag which indicates whether the information unit is a first type having a single word or a second type having a plurality of words; addressing means for selecting a memory location storing a word of an old information unit; register means for temporarily storing a new information unit to be stored in memory; means for obtaining the tag of the word in the memory location selected by said addressing means; means responsive to the tag of the word obtained from memory for indicating the type of word formerly stored in the selected memory location; means responsive to said indication for storing in the selected memory location a word contained in said register means together with a tag of the same type as that formerly in the selected memory location.
 20. In a data processing system as defined in claim 19 wherein the information unit of the second type is two words in length and said addressing means comprises an address register which can be incremented, and additionally comprising means operative in response to an indication that the word obtained from the memory location selected by the address register is of the second type for incrementing said address register and means for storing a second word of the new information unit into the memory location selected by the address register as incremented.
 21. In a data processing system as defined in claim 19 comprising means operative in response to the tag contained in the new information unit stored in said register means for indicating whether the new information unit is of the first type or of the second type; means operative in response to indications that the word obtained from the memory location selected by the address register is of the second type and the new information unit is of the first type for converting the new information unit to two words in length, means for incrementing the address register, means for storing the two words of the converted information unit into the memory locations identified by the address register before and after incrementing.
 22. In a data processing system as defined in claim 19 comprising means responsive to the tag contained in the new information unit for indicating the type of information unit, means operative in response to indications that old information unit is of the first type and the new information unit is of the second type for changing the tag of the new information unit to the first type of tag, and means for storing a word of the new information unit together with the changed tag in the memory location selected by the address register.
 23. In ad data processing system for Storing information units into memory, the combination comprising: memory means having a plurality of addressable memory locations for storing information units word by word, each information unit comprising at least one word and having an associated tag in at least one word, a first type of tag identifying the information unit as a single word type and a second type of tag identifying the information unit as a double word type; register means for temporarily storing new information units which are to replace old information units stored in said memory; means for indicating whether the old information unit contains an old tag of the first type or of the second type; means for indicating whether the new information unit contains a new tag of the first type or of the second type; means operative in response to indications that said tags are of the same type for replacing the old information unit with the new information unit; means operative in response to indications that the old tag is of the second type and that the new tag is of the first type for converting the new information unit from the first type to its equivalent information unit of the second type and means for replacing the old information unit with the converted new information unit; and means operative in response to indications that the old tag is of the first type and that the new tag is of the second type for converting the new information unit to an information unit of the first type and for replacing the old information unit with the converted information unit.
 24. In a data processing system as defined in claim 23 wherein the old tag indicating means comprises comparing means for indicating whether the old tag differs from the new tag.
 25. In a data processing system as defined in claim 23 wherein the new tag indicating means comprises comparing means for indicating whether the tag differs from the new tag. 